1. Field of the Invention
The present invention relates to a technology of delay analysis support for circuits.
2. Description of the Related Art
With miniaturization of large-scale integrations (LSI) in recent years, influence of statistical factors, such as process variation, reduction of supply voltage, and crosstalk, has become large, and a variation in circuit delay has been increasing. In a conventional static timing analysis (STA), a delay margin is secured for such a variation in circuit delay. Because of increase of the delay margin, timing design has become difficult.
For this reason, a demand for statistical static timing analysis (SSTA) increases in which an unnecessary delay margin is reduced by estimating circuit delay considering the statistical factors. As a method of SSTA, there is a block-based analysis, for example. In the block-based analysis, a circuit graph is topologically scanned, and a delay distribution of each node in the circuit graph is statistically acquired. By this block-based analysis, the entire circuit can be analyzed speedily.
On the other hand, by the block-based analysis, it is considerably difficult to acquire a true delay distribution of a node at which multiple signals run together. Therefore, the delay distribution of the node is approximately estimated using a statistical MAX operation. However, an estimation error by the statistical MAX operation can become large. As a result, accuracy of the delay analysis is deteriorated.
A method of enhancing the estimation accuracy of the statistical MAX operation performed in the block-based analysis has been disclosed in, for example, Proc. of the Design Automation Conf., pages 331-336, 2004, titled “First-order incremental blockbased statistical timing analysis” by C. Visweswariah, et al.; Proc. Intl. Conf. on computer-Aided Design, pages 621-625, 2003, titled “Statistical timing analysis considering spatial correlations using a single pertlike traversal” by H. Chang, et al.; and Proc. of the 12th Asia and South Pacific Design Automation Conf., pages 462-467, 2007, titled “New Block-based Statistical Timing Analysis Approaches without Moment Matching” by H. Zhou, et al.
However, in the conventional technique described above, to accurately acquire the delay distribution of the node at which multiple signals run together, complicated calculation is required, and the high speed property of the block-based analysis can be set off thereby. As a result, time required for the delay analysis increases, leading to increased design period.
Monte Carlo simulation, which enables to estimate the circuit delay accurately, is applicable instead of the block-based analysis. However, it is assumed that calculation time and an amount of memory exponentially increase with the scale of a circuit. Accordingly, application to a large scale circuit is difficult.